Bulldog
01-22-2008, 03:52 AM
Explaining Core 2's FSB, RAM, and bandwidth
Today, Icrontic.com has a crash course in the workings of the Core 2's front side bus, memory, and bandwidth. Aimed at novice overclockers, or anyone wondering why Intel rigs don't overclock like the Athlons of the past, the guide breaks down in plain English what could otherwise be a confusing, muddled topic.
"Today, Icrontic serves up a crash-course in the mysterious relationship of the Core 2 front side bus, RAM and bandwidth. The nature of the Core 2's design may be baffling, particularly to users exiting the era of synchronized Athlon XP buses, and we intend to cut through the haze and serve it straight just as we like to."
The link: http://icrontic.com/articles/core2_fsb_explained
Today, Icrontic.com has a crash course in the workings of the Core 2's front side bus, memory, and bandwidth. Aimed at novice overclockers, or anyone wondering why Intel rigs don't overclock like the Athlons of the past, the guide breaks down in plain English what could otherwise be a confusing, muddled topic.
"Today, Icrontic serves up a crash-course in the mysterious relationship of the Core 2 front side bus, RAM and bandwidth. The nature of the Core 2's design may be baffling, particularly to users exiting the era of synchronized Athlon XP buses, and we intend to cut through the haze and serve it straight just as we like to."
The link: http://icrontic.com/articles/core2_fsb_explained